The success of high-k metal-gate (HKMG) in the 45 nm technology node has made it key to the process flow for the sub-30 nm technology node. Intel, who has committed to a metal-gate-last approach, is now the leader in mass production of 45 nm and 32 nm chips. And former IBM alliances such as Sumsung, TSMC and Infineon have recently switched from gate-first to gate-last.
In the gate last technology, after performing high temperature ion implant anneal, polycrystalline silicon dummy gates have to be removed, and then high-k and metal gate materials are filled in, as can be seen from the flow in FIG. 1. A pad layer 2 of silicon oxide and a dummy gate layer 3 of polycrystalline silicon are deposited in silicon substrate 1, as shown in FIG. 1A. Gate stack structures are formed by etching. Silicon nitride is deposited and etched to form sidewall spacers 4. Then an interlayer dielectric layer (ILD) 5 of silicon oxide is deposited and is planarized by Chemical Mechanical Polishing (CMP). The dummy gate layer 3 of polycrystalline silicon is removed by means of wet etching with KOH or TAMH following the CMP, and the pad layer 2 is removed preferably by using HF or buffer oxide etch (BOE), as shown in FIG. 1B. Thus, gate trenches are formed. The gate trenches are filled with a high-k gate insulation layer 6 and a gate material layer 7 sequentially and CMP follows, as shown in FIG. 1C.
With the device size scaling down continuously, especially for technical nodes of less than 45 nm, the gate trenches width smaller than 50 nm after removing polycrystalline silicon dummy gates, a depth smaller than 100 nm, and a aspect ratio usually greater than or equal to 1.5. Such rectangular gate trenches with a large aspect ratio and a small size present great challenges to the subsequent high-k and metal gate material filling process in terms of coverage, density and uniformity.
Therefore, there is an urgent need for a method for filling the gate trenches effectively and uniformly.